The GOA (Gate Driver on Array) technology, i.e. the array substrate row driving technology is to utilize the array manufacture process of the Thin Film Transistor (TFT) liquid crystal display to manufacture the gate driving circuit on the Thin Film Transistor array substrate for realizing the driving way of scanning the gates row by row. It possesses advantages of reducing the production cost and realizing the panel narrow frame design, and is utilized by many kinds of displays. The GOA circuit has two basic functions: the first is to output the scan driving circuit for driving the gate lines in the panel to activate the TFTs in the display areas and to charge the pixels; the second is the shift register function. When the output of the Nth scan driving signal is accomplished, the output of the N+1th scan driving signal is performed with the control of the clock signal, and the transfer carries on in sequence.
With the development of Low Temperature Poly-Silicon (LTPS) semiconductor thin film transistor, the LTPS TFT liquid crystal display gradually becomes the focus that people pay lots of attentions. Because the silicon crystallization of the LTPS has better order than the amorphous silicon, and the LTPS semiconductor has ultra high carrier mobility, the liquid crystal display utilizing the LTPS TFT possesses advantages of high resolution, fast response speed, high brightness, high aperture ratio and et cetera. Correspondingly, the peripheral circuit around the LTPS TFT liquid crystal panel also becomes the focus that people pay lots of attentions.
FIG. 1 shows a CMOS GOA circuit according to prior art, comprising a plurality of GOA units which are cascade connected. The CMOS GOA circuit according to prior art does not only possess the basic scan driving function and the shift register function but also has a function of raising all the scan driving signals of the respective stages up to high voltage levels at the same time.
N is set to be positive integer, and the Nth GOA unit comprises: an input control module 100, a latch module 300, a signal process module 400 and an output buffer module 500.
The input control module 100 receives a stage transfer signal Q(N−1) of the GOA unit circuit of the former stage, a first clock signal CK1, a first inverted clock signal XCK1, a constant high voltage level signal VGH and a constant low voltage level signal VGL, and is employed to input the signal P(N) which the voltage level is opposite to the stage transfer signal Q(N−1) of the GOA unit circuit of the former stage into the latch module 300;
The latch module 300 comprises a inverter F to invert the signal P(N) and obtains the stage transfer signal of the GOA unit circuit of the Nth stage, and the latch module 300 performs latch to the stage transfer signal Q(N);
The signal process module 400 receives the stage transfer signal Q(N), a second clock signal CK2, the constant high voltage level signal VGH, the constant low voltage level signal VGL and the global signal Gas, and the signal process module 400 is employed to implement NAND logic process to the second clock signal CK2 and the stage transfer signal Q(N) to generate a scan driving signal G(N) of the GOA unit circuit of the Nth stage; implements NOR Logic process to the global signal Gas with a result of implementing AND logic process to the second clock signal CK2 and the stage transfer signal Q(N) to realize that the global signal Gas controls all the scan driving signals G(N) of the respective stages raised up to high voltage levels at the same time. Furthermore, as the global signal Gas is high voltage level, all the scan driving signals G(N) of the respective stages are raised up to high voltage levels at the same time;
The output buffer module 500 is electrically couple to the signal process module 400 and employed to increase a driving ability of the scan driving signal G(N) and to reduce the RC loading in the signal transmission procedure.
In the aforesaid CMOS GOA circuit according to prior art, as achieving the All Gate On function, there is the scan driving signal holding issue. Therefore, the reset and clear process to the voltage level has to be implemented to the stage signal and the scan driving signal before the GOA circuit normal functions. Thus, the GOA unit of the every stage in the CMOS GOA circuit according to prior art further comprises a reset module 200. As shown in FIG. 1, the GOA unit of the Nth stage is illustrated. The reset module 200 further comprises a P-type TFT. The gate of the P-type TFT receives the reset signal Reset, and a source receives a constant high voltage level signal VGH, and a drain is coupled to an input end of the inverter T in the latch module 300. When the reset signal Reset is inputted with a low voltage level, the P-type TFT is conducted, and the inverter F inverts the constant high voltage level signal, and thus pulls down the voltage level of the stage transfer signal Q(N) to clear and reset the stage transfer signal Q(N). The independent reset module 200 can raise the performance of the circuit but the additional components, wirings and signals increase the area of the GOA circuit and raise the complexity of the signals, which makes against the design of narrow frame panel.
Besides, in All Gate On period, except the global signal Gas, the constant high voltage level VGH and the constant low voltage level VGL, all of the rest signals are in floating state to reduce the standby power consumption of the entire circuit. Then, the voltage levels of respective nodes in the circuit are not determined, either. When the GOA circuit reboots and starts to function normally, there is high possibility to cause the failure of the circuit.